Most digital integrated circuits (“IC”s) of sufficient complexity use a clock signal in order to synchronize different parts of the circuit. The signal should cycle at a rate less than the worst-case internal propagation delays. In some cases, more than one clock cycle is required to perform a predictable action. As ICs become more complex, the problem of supplying accurate and synchronized clocks to all the circuits becomes increasingly difficult.
For complex ICs, a clock distribution network distributes the clock signal from a common point to all the elements that need it. The most effective way to get the clock signal to every part of a chip that needs it, with the lowest skew, is a metal grid that drives a “clock tree”. Since this function is vital to the operation of a synchronous system, much attention during the design of the IC is typically given to the characteristics of these clock signals and the electrical networks used in their distribution. In a large microprocessor, the power used to drive the clock signal can be over 30% of the total power used by the entire chip. The entire structure including gates and amplifiers generally have to be loaded and unloaded every cycle.
When designing ICs, in the physical layout stage where the parasitics are extracted, it has become increasingly difficult to debug the complex clock trees, in particular for clock trees with unknown structures. These clock trees typically include thousands of gates, and after extraction the total number of linear and non-linear devices can be in the millions. Because of this complexity, it has become very difficult for the IC designers to tweak or modify the clock tree if the result of the simulation does not meet the specification. In general, known IC design methods perform these modifications by analyzing the clock tree in its native form, which is a text-based file that includes an enormous amount of details to review.